This task is to implement the algorithm designed in WBS 1.6.6.1 in firmware for the FPGA on the DCRC (WBS 1.5.2). This first version is expected to target Rev D of the DCRC, the Altera Cyclone IV. This task requires the use of Altera’s CAD software, and the trigger firmware must be integrated into the more general board control firmware.
Resources
- Trigger Firmware Project Page (WBS 1.6.6.2)
- SuperCDMS SNOLAB Conceptual Design Report (Section 9.3.2) (Completed March 17, 2015)
- Trigger Firmware Design as implemented (Last updated Jun 2018)